Cypress Semiconductor /psoc63 /LPCOMP /CMP1_CTRL

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Interpret as CMP1_CTRL

MODE1=OFF, INTTYPE1=DISABLE

Description

Comparator 1 control Register

Fields

MODE1	Operating mode for the comparator 0 (OFF): Off 1 (ULP): Ultra lowpower operating mode (uses less power, < 300nA), must be used for DeepSleep or Hibernate. Only in this mode a local iref will be used. 2 (LP): Low Power operating mode (uses more power, <10uA @@@ TBD). In this mode the iref from SRSS will be used. 3 (NORMAL): Normal, full speed power operating mode (uses <150uA). In this mode the iref from SRSS will be used.
HYST1	Add 30mV hysteresis to the comparator 0= Disable Hysteresis 1= Enable Hysteresis
INTTYPE1	Sets which edge will trigger an IRQ 0 (DISABLE): Disabled, no interrupts will be detected 1 (RISING): Rising edge 2 (FALLING): Falling edge 3 (BOTH): Both rising and falling edges
DSI_BYPASS1	Asynchronous: bypass comparator output synchronization for DSI output: 0=synchronize (level or pulse), 1=bypass (output async). Note that in DeepSleep mode this bit needs to be set to observe the DSI output on the dedicated pin.
DSI_LEVEL1	Synchronous comparator DSI (trigger) output : 0=pulse, 1=level

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